Journal Article


Chris Bleakley
J.A. Maestro
P. Reviriego



reliability power consumption high level protection technique error correcting codes reliability analysis built in current sensors fault tolerant memory

Reliability Analysis of Memories Protected with BICS and a per-Word Parity Bit (2010)

Abstract This paper presents an analysis of the reliability of memories protected with Built-in Current Sensors (BICS) and a per-word parity bit when exposed to Single Event Upsets (SEUs). Reliability is characterized by Mean Time to Failure (MTTF) for which two analytic models are proposed. A simple model, similar to the one traditionally used for memories protected with scrubbing, is proposed for the low error rate case. A more complex Markov model is proposed for the high error rate case. The accuracy of the models is checked using a wide set of simulations. The results presented in this paper allow fast estimation of MTTF enabling design of optimal memory configurations to meet specified MTTF goals at minimum cost. Additionally the power consumption of memories protected with BICS is compared to that of memories using scrubbing in terms of the number of read cycles needed in both configurations.
Collections Ireland -> University College Dublin -> College of Science
Ireland -> University College Dublin -> School of Computer Science
Ireland -> University College Dublin -> Computer Science Research Collection

Full list of authors on original publication

Chris Bleakley, J.A. Maestro, P. Reviriego

Experts in our system

Chris Bleakley
University College Dublin
Total Publications: 105