Journal Article


J.A. Maestro
Chris J. Bleakley
P. Reviriego
Salvatore Pontarelli


Computer Science

computational complexity complex multiplication digital signal processing delay complexity concurrent error detection code fault tolerance

Low Complexity Concurrent Error Detection for Complex Multiplication (2013)

Abstract This paper studies the problem of designing a low complexity Concurrent Error Detection (CED) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits. Five novel CED architectures are proposed and their computational complexity, area, and delay evaluated in several circuit implementations. The most efficient architecture proposed reduces the number of gates required by up to 30 percent when compared with a conventional CED architecture based on Dual Modular Redundancy. Compared to a Residue Code CED scheme, the area of the proposed architectures is larger. However, for some of the proposed CEDs delay is significantly lower with reductions exceeding 30 percent in some configurations.
Collections Ireland -> University College Dublin -> School of Computer Science
Ireland -> University College Dublin -> Computer Science Research Collection

Full list of authors on original publication

J.A. Maestro, Chris J. Bleakley, P. Reviriego, Salvatore Pontarelli

Experts in our system

Chris Bleakley
University College Dublin
Total Publications: 105