Conference Proceedings


Brian Murray
Chris J. Bleakley
Jose Rodriguez
Vincent Berg


Computer Science

digital signal processing architecture single very large scale integration vlsi digital subscriber line dsl dsp class interface

A DSP Coprocessor for ADSL Lite (1999)

Abstract This paper presents Massana's DSP co-processor solution – FILU-DMT [1] for enabling soft G.Lite (or ADSL Lite) on Pentium and RISC processors. The user interacts with the coprocessor via a C API which accesses a shared RAM interface. All of the G.Lite DSP functions are pre-programmed and held in ROM. The FILU-DMT is implemented in fully synthesizable Verilog RTL with a single synchronous clock for high scan coverage. It is based on a dual MAC architecture which can perform a radix-4 FFT butterfly in 8 cycles yielding a 256 point FFT in 21 µs. This is the industry's fastest FFT for this class of processor. The FILU-DMT supports block floating-point arithmetic which achieves near floating-point performance at a fraction of the area cost of conventional DSPs.
Collections Ireland -> University College Dublin -> School of Computer Science
Ireland -> University College Dublin -> Computer Science Research Collection

Full list of authors on original publication

Brian Murray, Chris J. Bleakley, Jose Rodriguez, Vincent Berg

Experts in our system

Chris Bleakley
University College Dublin
Total Publications: 105